I. Field of the Disclosure
The technology of the disclosure relates generally to clock adjusting circuits and related circuits, systems, and methods that provide a clock signal to circuits, including but not limited to synchronous digital circuits.
II. Background
Synchronous digital circuits, such as central processing units (CPUs) or digital signal processors (DSPs) as examples, require a clock signal to coordinate timing of logic in the circuit. The frequency of the clock signal controls the switching speed or rate of the logic and thus the performance of the circuit. While it is generally desired to maximize performance by maximizing the frequency of the clock signal, synchronous digital circuits have maximum performance rates beyond which they will not operate properly. Thus, the frequency of the clock signal is controlled to operate within maximum frequency guidelines according to the performance of the components included in the circuit.
Ideally, the frequency of the clock signal would be set to the maximum performance rate of the circuit. However, in operation, the maximum performance rates of synchronous digital circuits and their components can vary and be lowered from ideal rates depending on a variety of conditions, which lead to performance loss. For example, variability in nanometer integrated circuit (IC) processes used to manufacture synchronous digital circuits and their components can cause delay variations. Environmental conditions, such as operating temperature and aging effect of transistors, can also affect performance. Voltage levels supplied by voltage suppliers can be momentarily lowered due to variations in current draw thus momentarily lowering performance as a result. In this regard, frequency generators are configured to control the maximum frequency of the clock signal according to worst case scenarios of the delay variations to provide proper circuit operation over all operating conditions. The delay variations resulting from process variations, temperature variations, and supply voltage variations may collectively be known as process voltage temperature (PVT) delay variations.
The difference between the ideal maximum frequency and the worst case frequency of the clock signal to account for worst case PVT delay variations during operation is known as clock rate margin or frequency margin.